Multiprocessing systems may share system resources including a cache memory and a translation lookaside buffer (TLB). When a processor makes a context switch, for example when a first process is swapped out of a processor and a second process is swapped into the processor, some state (e.g., working set data) associated with the process being swapped out may typically be cast out of fast memory (e.g., cache memory). By way of illustration, cache entries and TLB entries associated with the process being swapped out may be discarded or written back to memory. Working set data of the process being swapped out may be cast out because cache memory locations and TLB entries may be scarce and may be needed by a process being swapped in. Since the cache entries and TLB entries are discarded, when that process is swapped back in it may need to recreate its working set. Thus, cache memory misses may occur even for memory locations previously the subject of a cache miss. These cache misses are part of performance penalties associated with context switching.
Cache entries may have been written as the result of a cache miss and TLB entries may have been established as the result of a TLB miss and/or physical/virtual address translation. Unfortunately, the time spent resolving a cache miss, resolving a TLB miss, and/or translating a physical/virtual address may be wasted when the cache entry and/or TLB entry are discarded when a process is unloaded in a multiprocessing system. Additionally, the process being swapped in will be “starting from scratch” with respect to some aspects of its working set including cache entries and TLB entries. Thus, for a process swapped out and in cache misses may need to be resolved time and time again, TLB misses may need to be resolved multiple times, and physical/virtual addresses may need to be translated over and over.